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    欢迎光临专业集成电路测试网~~欢迎加入IC测试QQ群:111938408

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    CHROMA 3380D 超大规模集成电路测试系统

    时间:2020-03-02 10:24来源:未知 作者:ictest8 点击:
    CHROMA  3380D 超大规模集成电路测试系统
    In order to cope with the IC testing trend of high-speed, numerous pins and complex functions in the future, the newest generation of

    Chroma's VLSI tester, 3380D/3380P/3380, have adopted a more flexible architecture with higher

    integration density and powerful functions. The 3380D/3380P/3380 test systems have 4 wires HD

    VI source and any-pins-to-any-site high parallel test (multi-sites test) functions (256 I/O pins to test

    256 ICs in parallel) that can meet the upcoming higher IC testing demands.

    The test systems also have built in all-in-one design (for Test Head only) to provide a small

    footprint/clear power ATE to become a very competitive price/performance ratio test system.

    The 3380P/3380 test systems entered the testing market in 2013 and have over 70 installed bases

    (2014/E) now in Greater China.VLSI TEST SYSTEM MOdEL 3380d KEY FEATURES


    ■ 50/100 MHz clock rate

    ■ 50/100 Mbps data rate

    ■ 256 I/O digital I/O pins

    ■ Up to 256 sites parallel testing

    ■ 32/64/128M pattern memory

    ■ Various VI source

    ■ Flexible HW-architecture (Interchangeable I/O, VI, ADDA,)

    ■ Real parallel trim/match function

    ■ Time & Frequency Measurement Unit (TFMU)

    ■ AD/DA test (16/24bits option)

    ■ SCAN test option (max 1G M/chain)

    ■ ALPG test option for embedded memory

    ■ STDF tools support

    ■ Test program/pattern converter (J750, D10, S50, E320, SC312, V7, TRI-6020)

    ■ User friendly Windows 7 environment

    ■ CRAFT C/C++ programming language

    ■ SW (Software) same as 3360 & 3360P

    ■ D-M Probe-card compatible with 3360P DM probe-card

    ■ C-M DUT-card compatible with 3360D/3360P C-M DUT-card(FT/CP)

    Standard Specification 3380d Clock Rate 50/100 Mhz Data Rate 50/100 Mbps Pin Channels 256 Pins Pattern Memory 32M(S) / 64 & 128M (option) Parallel Testing Capability 256 DUTs EPA ± 500ps Resource Per Pin Architecture Yes VI source 8CH : MXDPS, 16CH : MLDPS-16(S) / MXUVI / MXREF, 32CH : MLDPS PMU(± 48V, ± 100 mA ) 16 Channels /board HV-Pins driver ( +5.9V to +13.5V ) 4 channels /board PPMU (-2V~+ 6V, ± 32 mA ) Per Pin (FIMV/FVMI) Programmable Active Load ( ± 12 mA) Per Pin TFMU (Time/Freq Measure unit:Max 400Mhz) Per Pin Free-run Clock ( Max: 200Mhz ) Per Pin Windows Environment Windows 7 Programming Language C/C++ 3380dTest Option Specification AD/DA Converter Test Option ( MXAWI/MXAWI2 ) 4 AWG/ 4 DIG ( 16/24bits) Mixed- Signal test option ( PXI ) 24bits, 200MS/s MXUVI ( DPS ± 12V, ± 1A, CG ± 4A ) 16 Channels /board MXDPS ( DPS ± 16V, ± 2A ) 8 Channels /board MXREF ( DPS ± 48V, ± 250mA, CG ± 1A ) 16 Channels /board MLDPS (DPS + 12V/± 500mA, ± 6V/± 1A , CG max ± 8 A ) 32 Channels /board SCAN Option 1G bits/ chain ALPG Memory Test Option 16X, 16Y, 16D /board 3380d System And dimension Power consumption Max 2KVA (VI Option to Max. 3KVA) Test Head W365 x D586 x H412 mm ( Max:45Kg) Power Box W220 x D372 x H187 mm ( Max:15Kg) 3380d Linking for Mass-Production S

    详细SPEC请下载参考:
    The 3380P IC Tester Specification

    3360 3380测试机程序开发培训可扫码观看:
     

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